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1 for more information www.linear.com/LTC4371 typical a pplica t ion fea t ures descrip t ion dual negative voltage ideal diode-or controller and monitor the lt c ? 4371 is a two-input negative voltage ideal diode-or controller that drives external n-channel mosfets as a low dissipation alternative to schottky diodes in high power C 48v systems. low power dissipation and voltage loss eliminates the need for heatsinks and reduces pc board area. power sources can be easily ored together to increase total system power and reliability. the LTC4371 tolerates 300v transients such as those experienced during lightning-induced surges and input supply short-circuit events. the internal shunt regulator and low 350a quiescent current allow the use of a large value dropping resistor to protect the supply pin against high voltage transients, while the high impedance drain pins can be similarly protected by high value series resis - tors without compromising diode operation. the 220ns reverse current turn-off is achieved by a power ful 2a gate driver with low propagation delay, thereby minimizing peak reverse current under catastrophic fault conditions. open mosfet and fuse faults are indicated at the faultb pin, which is capable of sinking 5ma to drive an led or opto isolator. a pplica t ions n controls n-channel mosfets to replace power schottky diodes n low 15mv forward voltage minimizes dissipation n withstands > 300v transients n fast turn-off: <220ns n shunt regulated for high voltage applications n 4.5v minimum operation n low 350a quiescent current n 5ma gate pull-up for 60hz applications n high impedance drain pins: <10a leakage n open fuse and mosfet monitor n 10-pin (3mm 3mm) dfn and msop packages n C48v telecom power n advancedtca systems n network routers and switches n computer systems and servers l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. C48v/50a diode-or power dissipation vs. load current 4371 ta01a LTC4371 da db gb ga sa v z v dd sb v ss faultb c1 2.2f r da 20k r db 20k m1* m3* m2* v a ?36v to ?72v v b ?36v to ?72v v out 50a load d1 green led = mosfets good r z 30k r1 33k rtn m4* *m1-m4: ipt020n10n3 lt c4371 4371f 10 20 30 40 50 0 10 20 30 40 mosfet power dissipation (w) vs load current 4371 ta01b (2?ipt020n10n3) schottky diode (sbrt60u100ct) power saved current (a) 0
2 for more information www.linear.com/LTC4371 top view dd package 10-lead (3mm 3mm) plastic dfn 10 11 9 6 7 8 4 5 3 2 1 db gb sb faultb v ss da ga sa v z v dd t jmax = 125c, ja = 43c/w (note 4) exposed pad (pin 11) pcb v ss connection optional 1 2 3 4 5 da ga sa v z v dd 10 9 8 7 6 db gb sb faultb v ss top view ms package 10-lead plastic msop t jmax = 125c, ja = 160c/w p in c on f igura t ion a bsolu t e maxi m u m r a t ings supply voltage v dd .................................... C 0.3 v to 17v input voltage da , db (note 3) .................................... C 4 0v to 100v sa , sb .................................................. C 0. 3v to 0.3v dc currents v z ...................................................................... 20m a da , db ............................................................... 1m a single pulse current ( 6ms ) da, db ........................ 10 ma (notes 1, 2) o r d er i n f or m a t ion output voltages ga , gb ................................................... C 0. 3v to v dd faultb .................................................. C 0. 3v to 17v operating ambient temperature range lt c4 371 c ................................................ 0 c to 70 c lt c4 371 i ............................................. C 40 c to 85 c storage temperature range .................. C 65 c to 150 c lead temperature (soldering, 10 sec) ms package ...................................................... 300 c lead free finish tape and reel part marking package description temperature range LTC4371cdd#pbf LTC4371cdd#trpbf lgsd 10-lead (3mm 3mm) plastic dfn 0c to 70c LTC4371idd#pbf LTC4371idd#trpbf lgsd 10-lead (3mm 3mm) plastic dfn C40c to 85c LTC4371cms#pbf LTC4371cms#trpbf ltgsf 10-lead plastic msop 0c to 70c LTC4371ims#pbf LTC4371ims#trpbf ltgsf 10-lead plastic msop C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. ( http://www.linear.com/product/LTC4371#orderinfo) lt c4371 4371f
3 for more information www.linear.com/LTC4371 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, i z = 50a, v dd = 12.4v, sa = sb = v ss unless otherwise noted. symbol parameter conditions min typ max units v dd input supply range l 4.5 16 v i dd input supply current normal operation gate fault to v ss , strong pull-up disabled gate fault to v ss, strong pull-up enabled ?v sd = 0.1v v z = 10.4v, ?v sd = 0.1v, one gate = v ss i z = 50a, ?v sd = 0.1v, one gate = v ss l l l 200 400 4.5 300 550 7 450 750 9.5 a a ma v z shunt regulator voltage i z = 50a l 11.8 12.4 14 v ?v z shunt regulator load regulation i z = 50a to 10ma l 600 mv v z(pu) v z high threshold to enable strong gate pull-up v dd = v z rising l 10.7 11.2 11.8 v ?v z(pu) v z high threshold hysteresis 0.5 v v z(pu) v z low threshold to enable strong gate pull-up v z falling l 1.15 1.25 1.35 v ?v sd source-drain forward servo voltage l 5 15 25 mv ?v gate gate drive (v g C v s ) i g = 0a, C1a; ?v sd = 100mv l v dd C 0.2 v dd + 0.1 v i gate(up) gate pull-up current ?v sd = 100mv, ?v gate = 5v l C3 C5 C8 ma i gate(dn) gate pull-down current strong gate pull-down current ? v sd = C10mv, ?v gate = 5v ?v sd = C100mv, ?v gate = 5v l l 7 1 10 2 13 3 ma a t off gate turn-off time in fault condition ?v sd = 0.1v step to C0.4v, c gate = 3.3nf, ?v gate <1v l 220 ns i d da, db leakage current mosfet off mosfet open v d = 80v v d = C40v l l 10 C10 a a r d da, db resistance ?v sd = C50mv to 0.1v l 1 2 5 m v bvd da, db breakdown voltage i d = 10ma, 6ms l 100 130 170 v i s sa, sb leakage current v s = 0v l 2 a ?v sd(flt) source-drain fault detection threshold l 150 200 225 mv v faultb faultb output low i faultb = 5ma l 0.4 v i faultb faultb leakage current v faultb = 16v l 1 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive; all voltages are referenced to v ss unless otherwise specified. note 3: an internal clamp limits the da and db pins to a minimum of 100v above v ss and C40v below v ss . this pin can be safely tied to higher voltages through a resistance that limits the current below 1ma dc or 10ma for a 6ms transient. driving this pin with current beyond the clamp may damage the device. note 4: thermal resistance is specified with exposed pad soldered to a 3-inch by 4.5-inch, four layer fr4 board. if exposed pad is not soldered ja = 93c / w. lt c4371 4371f
4 for more information www.linear.com/LTC4371 typical p er f or m ance c harac t eris t ics turn-off time vs initial overdrive turn-off time vs final overdrive (t off vs v final , v initial = 0.1v) load current vs forward voltage turn-off time vs gate capacitance gate current vs forward voltage drain current vs drain voltage drain current vs drain voltage supply current shunt regulator load regulation t a = 25c, unless otherwise noted. 85c 25c ?40c 85c 25c ?40c lt c4371 4371f 200 10 20 30 40 50 0 100 200 300 400 300 t off (ns) gate capacitance 4371 g07 v dd = 12.4v ?v sd = v initial to ?0.4v v initial (v) 0 0.2 0.4 0.6 400 0.8 1 0 50 100 150 200 250 t off (ns) initial overdrive i dd (ua) 4371 g08 v dd = 12.4v ?v sd = 0.1v to v final v final (v) 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1 0 4371 g01 50 100 150 200 250 t off (ns) final overdrive 4371 g09 i z (ma) 0.01 0.1 1 10 v dd (v) 100 12.25 12.38 12.50 12.63 12.75 v z (v) shunt regulator load regulation 4371 g02 ?v sd (mv) 0 0 15 30 45 60 15 0 ?15 ?30 ?45 4 i gate (a) vs forward voltage drop 4371 g03 v dd = 12.4v v d (v) ?40 0 40 80 ?0.2 8 ?0.1 0 0.1 2.5 5 7.5 10 i d (a) 4371 g04 12 v dd = 12.4v v d (v) ?0.50 ?0.25 0 0.25 0.50 0.75 16 ?200 0 200 400 i d (na) 4371 g05 ipt020n10n3 (2) 0 ?v sd (mv) 0 10 20 30 40 0 10 20 30 100 40 50 load current (a) vs forward voltage drop 4371 g06 v dd = 12.4v ?v sd = 0.1v to ?0.4v ?v gate 1v c gate (nf) 0
5 for more information www.linear.com/LTC4371 p in func t ions da, db (pins 1 and 10): drain voltage kelvin sense in - puts. da and db connect to the drains of the n-channel mosfet s. the voltage sensed by sa C da and sb C db is used to control the gate drive and hence the ?v sd drop across the mosfets, and it is also used for fault detection. for accurate kelvin sensing of ?v sd , connect these pins as closely as possible to the mosfet drains. an external resistor protects the da and db pins from transients ex - ceeding 100v . if the LTC4371 is used in a single channel application, da and db may be joined together and operated in parallel; otherwise connect the unused drain pin to v ss . exposed pad (pin 11 C dd package only): exposed pad may be left open or connected to v ss . faultb (pin 7) : fault output. open drain output that pulls low to indicate that one or both of the external mosfets have failed open. faultb can sink up to 5ma to drive an opto isolator or led. the maximum allowable pull-up voltage is 17v. connect to v ss if unused. ga, gb (pins 2 and 9): gate drive outputs. ga and gb operate between v ss and v dd to control their associated mosfet gates and emulate the behavior of a diode. for ?v sd >15mv , the gate pin drives the mosfet on, while ?v sd <15mv produces the opposite effect. with a large positive ?v sd , the gate pin pulls up with a strong 5ma source, while large negative ?v sd activates a 2a pull- down with a maximum propagation delay of 220ns . if the LTC4371 is used in a single channel application, the gate pins may be joined together and operated in parallel to realize a two-fold increase in gate drive strength; otherwise the unused gate pin may be left open. sa, sb (pins 3 and 8): source voltage kelvin sense in - puts. sa and sb connect to the sources of the n-channel mosfet s. the voltage sensed by sa C da and sb C db is used to control the gate drive and hence the ?v sd drop across the mosfets, and it is also used for fault detection. for accurate kelvin sensing of ?v sd , connect these pins as close as possible to the mosfet sources. if the LTC4371 is used in a single channel application, sa and sb may be joined together and operated in parallel; otherwise connect the unused source pin to v ss . v dd (pin 5): positive supply voltage input. supply v dd directly from 4.5v to 16v, or in shunt regulated applica - tions connect directly or through a buffer transistor biased by? v z . when connected directly to v z , bypass v dd with 2.2 f to v ss . maximum gate drive voltage is limited to v dd . v ss (pin 6): device substrate and negative supply volt- age. v ss connects to v out at the joined sources of the n-channel mosfets. v z (pin 4): shunt regulator supply input. this pin serves as a shunt regulator for the v dd pin or as a regulator refer - ence, and operates with a bias of 50a to 10ma. bypass with at least 100nf when used as a reference, and 2.2f when connected to the v dd pin. if unused, connect v z to v ss . see strong gate pull-up in the applications infor - mation for details on the relationship between the v z pin voltage and gate pin drive strength. lt c4371 4371f
6 for more information www.linear.com/LTC4371 b lock diagra m da ga sa 60v 130v ampa 15mv db gb sb 60v 130v ampb 15mv r z rtn v z v dd 12.4v v out v ss m2 fault detection faultb m1 v a v b r da r db 4371 bd ? + ? + +? +? lt c4371 4371f
7 for more information www.linear.com/LTC4371 o pera t ion the LTC4371 controls n-channel mosfets to emulate two ideal diodes (see block diagram). by sensing the mosfet s source-to-drain voltage drop, amplifiers ampa and ampb control the gate of their respective external mosfet to act as an ideal diode with a 15mv forward (?v sd ) drop. with low load currents, the amplifier regulates the mosfet gate near its threshold to maintain a forward drop of 15mv. as load current increases, the gate voltage is driven higher to maintain a drop of 15mv . for very large load currents where the mosfet gate is driven fully on, the forward drop rises linearly with current according to r ds(on) ? i load . if the forward drop is less than 15mv, or if ?v sd reverses, the amplifier turns the mosfet off and the load current transfers to the other channel. when the power supply voltages are nearly equal, this regulation technique ensures that the load current is smoothly shared between the supplies without oscilla - tion. the current balance depends on the r ds(on) of the mosfets and the output resistance of the supplies. in the case of supply failure, such as supply v a , while conducting most or all of the load current is shorted to return, a large reverse current flows from return through m1 to any load capacitance and through m2 to supply?v b . ampa detects the current reversal and turns off m1 in less than 220ns . fast turn-off prevents reverse current from rising to a damaging level. the remaining supply v b delivers load current through the body diode of m2, until the gate is driven on. with 700mv forward drop across m2, ampb responds quickly and drives the gate with 5ma pull-up current, limiting the body diode conduction time to under 100s. this minimizes power dissipation arising from switchover and is especially important in 60hz ac applications. as the forward drop reduces, a weaker output stage takes over and regulates the forward drop, within the limitations of r ds(on) , to 15mv. the LTC4371 can be powered in C4.5v to C16v applica - tions by connecting v dd directly to the power supply return. in higher voltage applications or to guard against input transients, v z and v dd can be connected together and powered from return through a bias resistor, r z . for repetitive 5ma gate pull-up current, v dd can be driven by a buffer biased by v z . the v z pin is shunt regulated to 12.4v with respect to v ss with 50a minimum bias, and is capable of sinking up to 10ma. the LTC4371 is designed to withstand high voltage tran - sients exceeding 300v , such as those experienced during lightning-induced surges and input supply short circuit events, without damage. 130v internal clamps protect drain pins da and db against positive spikes. external resistors r da and r db are necessary to limit the peak clamp current to less than 10ma. in an application circuit, negative spikes are clamped by the mosfets body diode to v out , such that the drain pin never sees more than C700mv with respect to v ss . a safely clamped negative transient on one input manifests itself as a positive transient on the second input and as an increased voltage from rtn to v out . the bias resistor, r z , limits the current into the v z shunt regulator to less than 10ma. a fault detection circuit monitors mosfet ?v sd ; faultb pulls low if ?v sd of either channel exceeds 200mv while the gate is driven fully on. this is an indication of an open circuit mosfet and can be configured for fuse monitor - ing by moving the drain pin connection to the input side of the fuse. lt c4371 4371f
8 for more information www.linear.com/LTC4371 a pplica t ions i n f or m a t ion figure 1. C36v to C72v/25a ideal diode-or controller figure 2. simplest solution: v dd connected directly to v z 4371 f01 LTC4371 da db ga gb sa v z v dd sb v ss c1 2.2f r da 20k r db 20k m1 ipt020n10n3 m2 ipt020n10n3 v a ?36v to ?72v v b ?36v to ?72v v out 25a load d1 green led r z 30k r1 33k rtn faultb LTC4371 v z v dd v ss c1 2.2f r z rtn v out 4371 f02 high availability systems employ parallel connected power supplies or battery feeds to achieve redundancy and enhance system reliability. schottky diodes are a popular means of oring these supplies together at the point of load. the chief disadvantage of schottky diodes is their sig - nificant forward voltage drop and resulting power and efficiency loss. this drop reduces the available supply voltage and dissipates significant power . the LTC4371 solves these problems by using an n-channel mosfet as a low loss pass element to emulate the behavior of a diode (see figure?1). the mosfet is turned on when power passes in the forward direction (positive current flow from source to drain), allowing for a low voltage drop from load to sup - ply. in the reverse direction, the mosfet is turned off to block current flow . by these means, the mosfet is made to approach the function and per formance of an ideal diode. the mosfet voltage drop, ?v sd , is sensed by the da and sa, or db and sb pins. powering v dd the LTC4371 is fundamentally a low voltage device op - erating over a range of 4.5v to 16v at the v dd pin, with respect to v ss . the gate amplifiers are powered from the v dd pin and pull-up to within 300mv of v dd . in low voltage applications such as C5v or C12v, the v dd pin can be powered directly from return, with v ss con- nected to v out . an internal 12.4v shunt regulator at the v z pin provides a means of operating the LTC4371 from higher voltage supplies. it regulates over a range of 50a to 10ma. in the simplest configuration shown in figure?2, v dd is connected directly to v z and biased by resistor r z from the return. a 2.2f decoupling capacitor is required to stabilize the v z shunt regulator, and to momentarily provide the 5ma fast pull-up current at the gate pins as needed. bias resistor r z is chosen to bias the shunt regulator and provide the maximum v dd current at the expected minimum input voltage according to: r z < v in(min) C v z(min) i dd(max) + 50a (1) maximum bias resistor dissipation is calculated from: p d(rz) = (v in(max) C v z(min) ) 2 r z (2) the maximum shunt regulator current must not exceed 10ma such that: r z > v in(max) C v z(min) 10ma (3) in C48v applications a single 1206 size 30k resistor is adequate to power the LTC4371. in the application shown in figure? 1, at 100v (a commonly specified maximum transient condition) peak dissipation in r z just exceeds 250mw, while the maximum v z current is slightly less than 3ma. dissipation rises in certain applications so that a larger package or multiple series units are necessary to imple - ment r z . examples include ac applications where the gate drivers demand additional current to supply repetitive lt c4371 4371f
9 for more information www.linear.com/LTC4371 a pplica t ions i n f or m a t ion figure 4. mosfet cascode for high voltage >?250v applications with 5ma gate pull-up current figure 3. v dd connected to v z with npn for repetitive 5ma gate pull-up current LTC4371 v z v dd v ss c1 0.1f r z rtn v out q1 4371 f03 4371 f04 LTC4371 v z v dd v ss c1 0.1f r z1 r z2 r g 10 rtn v out q1 2n3904 m1 bsp125 (600v) pulses from the 5ma fast pull-up, applications where the input operating voltage exceeds 72v and applications with a wide range of input voltage, particularly those where the minimum input voltage approaches the operating voltage of the LTC4371. a wide input voltage range may also result in a situation where the maximum v z current calculated in equation 3 exceeds 10ma. for these cases an npn transistor can be used to buffer the shunt regulator and power ?v dd , as shown in figure?3. equation 1 becomes: r z < v in(min) C v z(min) 50a + i dd(max) (4) r z (or r z2 ) may be split into multiple segments in order to achieve the desired standoff voltage or dissipation. whereas 1206 size resistors are commonly rated for 200v working and 400v peak, pad spacing and circuit board de - sign rules may limit the working rating to as little as 100v. in figure? 3, the voltage drop and power dissipation of q1 may be augmented by the use of one or more resistors in series with the collector. the same applies for m1 in figure?4. for all applications r z (or r z1 + r z2 ) must limit the maxi- mum v z current to less than 10ma, as calculated using equation 3. if voltage transients are anticipated, v in(max) becomes the peak transient voltage. transient require - ments may force the use of figure?3 or figure?4 instead of figure? 2. the peak v z current may also be reduced to less than 10ma by filtering, e.g. split r z (or r z2 ) into two equal parts and connect a bypass capacitor from the central node to v ss . strong gate pull-up for fast turn-on, a strong 5ma driver pulls up on the gate when the mosfet forward drop ( ?v sd ) is large. in simple shunt-regulated applications such as shown in figure?2, the bias resistor r z may be incapable of supplying 5ma. in this case, a 2. 2f bypass capacitor is required to momentarily provide the strong pull-up current to fully charge the mosfet gate. in normal operation the 5ma drive is not a dc condition, as it flows only long enough to deliver gate charge to the mosfet. the amount of where 50a represents the minimum v z shunt regulator operating current and is q1s dc current gain. the maximum power dissipation in r z and the maximum v z current are calculated from equations 2 and 3. dissipa - tion in emitter follower q1 is given by: p d(q1) = (v in(max) + v be C v z(min) ) ? i dd(max) (5) in buffered applications, bypass v z with a 100nf capacitor to v ss . bypassing v dd is unnecessary. for applications at very high voltages, beyond 300v, small high voltage mosfets are more readily available than bipolar devices and the circuit of figure?4 is preferred. r z , calculated using equation 4, is split into two parts, r z1 and r z2 . r z1 is sized to produce a 3v drop when operating at v in(min) . lt c4371 4371f
10 for more information www.linear.com/LTC4371 a pplica t ions i n f or m a t ion figure 5. mosfet follower for high voltage >?250v applications with 5ma gate pull-up current disabled charge is approximately equal to the total gate charge, q g , as specified on the mosfet s data sheet. if there is a fault wherein the mosfet gate is shorted to v ss and ?v sd is large, the 5ma pull-up becomes a continuous load on v dd . the extra v dd current overwhelms r z and discharges the 2.2f bypass capacitor. when v z falls to the v z(pu_en) threshold of 10.7v , the 5ma pull-up current on both channels is disabled. the 5ma pull-up is enabled when v z recovers to 11.2v . this feature prevents a shorted gate pin from collapsing v dd and, aside from disabling the 5ma pull-up, interfering with the operation of the second channel when using the configuration shown in figure?2. in applications such as figure?3 and 4, if the v dd supply is designed to deliver >?5ma, no v dd bypassing is required. note that a shorted gate will demand a continuous current of 5ma whenever ?v sd is large. the 5ma pull-up is enabled when v z is biased to >11.8v in its normal shunt regulator mode, or when v z is <1.15v. connecting v z to v ss permanently enables the 5ma gate pull-up. if v z is not used as a shunt regulator, the 5ma pull-up can be disabled by biasing v z to voltage between 1.35v and 10.4v (with respect to v ss ) as shown in figure?5. the range of 11.6v to 14.1v , compatible with standard 10v -specified mosfets. in low voltage applications, such as where the v dd pin is directly powered from less than 10v , the gate drive is compatible with logic-level and sub logic-level mosfets. the drain-source breakdown rating, bv dss , must be greater than or equal to the highest input supply voltage. if an input is shorted, the full supply voltage of the opposing channel will appear across the mosfet of the shorted channel. avalanche may occur during input short circuits and lightning induced surges if the peak transient voltage exceeds bv dss with respect to v out . the LTC4371 attempts to servo the forward drop across the mosfet (?v sd ) to 15mv by controlling the gate, and flags a fault if the drop exceeds 200mv when the mosfet is driven fully on. thus an upper bound for r ds(on) is set by: r ds(on) < ?v sd(flt) i load(max) (6) where ?v sd(flt) is 150mv minimum. further, r ds(on) must be small enough to conduct the maximum load current without excessive mosfet dis - sipation, which is calculated from: p d(mosfet) = i load(max) 2 ? r ds(on) (7) the definition of excessive is provided by the circuit designer based on package and circuit board thermal constraints. loop stability the gate amplifiers are compensated by the input capaci - tance of the external mosfets. no further compensation components are necessar y except in the case of very small mosfets. if c iss is less than 500pf, add a 1nf capacitor across the mosfet gate and source terminals. high voltage transient protection although the LTC4371 drain pins, da and db are designed to handle voltages ranging from C40v to 100v with respect to v ss , they may be subjected to much higher voltages, even in C48v systems. da and db are directly exposed to mosfet selection the LTC4371 drives n-channel mosfets to conduct the load current. the important features of the mosfets are threshold voltage, v gs(th) ; maximum drain-source voltage, bv dss ; and on-resistance, r ds(on) . full gate drive for the mosfets ( ?v gate ) is v dd ?+? 100mv /C 200mv . when used in shunt regulated circuits such as shown in figure?2, full gate drive lies in LTC4371 v z v dd v ss d2 7.5v r z 510k c1 10nf rtn v out m1 bsp125 d1 7.5v c2 10nf 4371 f05 r g 10 lt c4371 4371f
11 for more information www.linear.com/LTC4371 a pplica t ions i n f or m a t ion figure 6. input short circuit parasitics and protection against high voltage transients 4371 f06 LTC4371 da db ga gb sa v z v dd sb v ss faultb 2.2f 20k 20k opt. v a ?36v to ?72v v b ?36v to ?72v v out green led = mosfets good r z 30k 33k rtn ? + + ? input parasitic inductance ? + output parasitic inductance input parasitic inductance input short c load reverse recovery current opt. all voltages appearing at the input. spikes and transients may arise from various conditions including lightning induced surges, electrostatic discharge, switching of adjacent loads, and input short circuits. the dynamic behavior of an active ideal diode entering reverse bias is most accurately characterized by a delay, followed by a period of reverse recovery. during the delay phase some reverse current is built up, limited by parasitic resistance and inductance. during the reverse recovery phase, energy stored in the parasitic inductance is trans - ferred to other elements in the circuit. current slew rates during reverse recover y may reach 100a /s or higher. high slew rates coupled with parasitic inductance in series with the input and output can cause destructive transients to appear at the drain, source and v ss pins of the LTC4371 during reverse recovery. a zero impedance short circuit directly across the input and return is especially troublesome because it permits the highest possible reverse current to build up during the delay phase. when the mosfet finally interrupts the reverse current, the mosfet drain and the LTC4371 drain pins experience a positive-going voltage spike, while the mosfet source and the LTC4371 source and v ss pins spike in the negative direction. to protect the circuit bias - ing v dd , clamp or bypass v out as close as possible to the junction of the mosfet sources and v ss and the point where the v dd bias circuit connects to return. the positive spike at the input is clamped to bv dss rela- tive to v out by mosfet avalanche. bv dss is inadequate protection for the da and db pins, as shall be discussed later. although the energy stored in parasitic inductance during input short circuit faults is at least two orders of magnitude smaller than the avalanche energy rating of most mosfets, the peak current may exceed the avalanche current rating of the mosfet. in this case and if positive- going transient energy from other external sources exceeds the mosfet s avalanche energy rating, add tvs clamps across each mosfet as shown in figure?6. externally applied input transients in the negative direc - tion are clamped by the body diodes of the mosfets to C 700mv with respect to v out , if not connected directly through r ds(on) to v out , and pose no particular hazard for the da and db pins. negative input transients couple directly to the output which increases the rtn to v out voltage. although the shunt resistor, r z , limits the current into v z to a safe level of less than 10ma, an output capaci - tor or tvs clamp may be required to protect downstream cir cuitr y from negative input transients. 100v bv dss(min) mosfets are commonly used in C48v applications, but bv dss(max) is not guaranteed and cannot be relied upon to protect the da and db pins from exceed - ing their absolute maximum rating of 100v. nevertheless, the 100v absolute maximum rating for da and db may be safely exceeded if certain precautions are taken. the internal 130v clamps shown in the block diagram tolerate lt c4371 4371f
12 for more information www.linear.com/LTC4371 a pplica t ions i n f or m a t ion figure 7. 300v drain pin protection figure 10. drain protection for applications up to C600v 4371 f07 LTC4371 da ga sa v ss r da 20k m1 v a v out figure 9. high voltage drain pin protection with c1 and r1 maintaining fast turn-off time 4371 f08 LTC4371 da ga sa v ss r da 100k r1 10k m1 v a v out c1 100pf 4371 f10 LTC4371 da ga sa v ss m2 bss127 m1 v a v out v z r z d1 in4148w figure 8. reverse response time vs. drain pin resistance up to 10ma for 6ms in breakdown. for protection against transients exceeding 100v, add series resistors r da and r db according to: r da , r db > v in(pk) C v bvd(min) 10ma (8) where v in(pk) is the peak input voltage measured with respect to v ss , and v bvd(min) is the minimum drain pin breakdown voltage (100v). because their presence incurs no particular performance penalty, a minimum value of 20k? is prudent and pro - tects the da and db pins against transients up to 300v, as shown in figure? 7. a practical limit for r da and r db is 100k ? , beyond which their resistance interferes with the operation of the gate amplifier. some speed penalty is incurred for values greater than 20k? , as shown in figure? 8. if the speed penalty is unacceptable, add a resistor and capacitor across r da and r db as shown in figure?9 to restore the response time. high voltage dc applications an extra blocking device is necessary to protect the da and db pins in applications where the dc input voltage exceeds 100v . even in C48v applications the equivalent dc input voltage may exceed 100v, as a result of a reverse connected supply feed that can impress up to double the maximum operating voltage across the inputs. because the 130v da and db pin clamps are limited to clamping short-term spikes, some other means of limiting the maximum applied voltage is necessary in dc applica - tions. the n-channel cascode shown in figure?10 extends the dc input operating voltage to 600v . it safely clamps the drain pin to about 2v less than v z , yet introduces only 500? series resistance when the input is in the vicinity of v out ; fast turn-off time is maintained. lt c4371 4371f 80 100 0 150 300 450 600 t off (ns) drain pin resistance 4371 f09 v dd = 12.4v ?v sd = 0.1v to ?0.4v c gate = 3.3nf drain pin resistance (k) 0 20 40 60
13 for more information www.linear.com/LTC4371 a pplica t ions i n f or m a t ion figure 11. fuse and open mosfet detection figure 12. back-to-back drain pin limiter for 600v fuse and open mosfet detection the LTC4371 monitors ?v sd of each channel as measured across sa C da and sb C db. if ?v sd of either channel exceeds 200mv and the associated gate pin is driven fully on, faultb pulls low to indicate a fault. conditions lead - ing to high ?v sd include excessive load current (i load r ds(on) ?> 200mv ), an open circuit mosfet or an open fuse placed in series with the mosfet. a high ?v sd fault is detected on only the highest voltage input supply, i.e. the path that should be supplying power is, as a result of one of the aforementioned conditions, unable to do so. temporary conditions, such as the initial 700mv drop experienced when an input first rises to the point of sup - plying current but before the gate has been driven on, are masked since the gate must also be high for fault detection. the ?v sd monitor can be used to detect open fuses, as shown in figure?11. an open fuse gives the same signa - ture as an open mosfet : ? v sd increases beyond 200mv when the affected input surpasses the opposing channel. the connection shown in figure? 11 introduces a new problem: an open fuse and open mosfet exposes the da and db pins to high negative voltage with respect to v ss . diodes d1 and d2 clamp the da, db pins from exceeding the absolute maximum of C40v with respect to v ss . figure?12 shows a protection method that extends da and db pin operation to 600v . the drain pins are clamped by an 82v zener diode. as shown, the da pin is clamped at 82v with respect to v ss in the positive direction, and 700mv below v ss in the negative direction. when a high input voltage of either polarity is present, back-to-back depletion mode n-channel mosfets limit the current in the zener diode to v gs(th) /r da (100a for r da = 20k), a value that is indefinitely sustainable. faultb pin the open drain faultb pin pulls low when the ?v sd of either channel exceeds 200mv, while its gate is driven fully on. faultb can sink 5ma to drive an led for visual indication, or an opto isolator to communicate across an isolation barrier. the faultb pin voltage is limited to 17v absolute maximum with respect to v ss in the high state and cannot be pulled up to return except in low voltage applications. in figure?13, the faultb pin is used to shunt current away from a green led; the led indicates (illuminates when) no fault condition is present. the operating voltage is limited at the low end by the minimum acceptable led current, and at the high end by the faultb pins 5ma capability. figure?14 shows a simple implementation driving a red led; the led indicates a fault condition is present. while this simple configuration works well in C48v applications, the maximum operating voltage is limited to 100v, the led 4371 f11 LTC4371 da db ga gb sa sb v ss r da 20k r db 20k m1 m2 v a ?36v to ?72v v b ?36v to ?72v v out d1 1n4148w d2 1n4148w f1 f2 4371 f12 LTC4371 da ga sa v ss m2* m3* m1 v a v out r da 20k 82v *m2, m3: bsp135 (600v) depletion nmos lt c4371 4371f
14 for more information www.linear.com/LTC4371 a pplica t ions i n f or m a t ion figure 13. faultb drives a green led in shunt mode figure 14. faultb drives a red led in series mode figure 15. faultb driving an led in a high voltage application figure 16. recommended pcb layout for m1, m2 and c1 c1 v out v b v a r db r da 4371 f16 m1 m2 LTC4371 4371 f13 LTC4371 v ss v out d1 green led = mosfets good r1 33k rtn faultb 4371 f14 LTC4371 v ss v out d1 red led = mosfet bad r1 20k 500mw r2 3.9k rtn faultb 4371 f15 LTC4371 v ss v dd v out ?600v max d1 red led = mosfet bad r2 10k m2 bsp125 rtn faultb current varies widely with operating voltage, and dissipation in the 20k resistor reaches 250mw at 72v input. these shortcomings are eliminated by the slightly more complex circuit shown in figure?15. a cascode shields the faultb pin from the high input voltage and dissipates no power under normal conditions, while the led current remains constant regardless of input voltage when indicating a fault. at 600v , cascode dissipation reaches 600mw maximum. layout considerations a sample layout for the LTC4371 dfn package and pg- hsof-8 mosfet package is shown in figure?16. the v dd bypass capacitor c1 provides ac current to the device; place it as close to v dd and v ss pins as possible. connect the gate amplifier input pins, da, db, sa and sb, directly to the mosfets drain and source terminals using kelvin connections for good accuracy. place the mosfet sources as close together as possible, with v ss connecting at their intersection. keep the traces to the mosfet drains and common source wide and short. a good rule-of-thumb for minimizing self-heating effects in the copper traces is to allow at least 1- inch trace width per 50 amperes, for a surface layer of 1- ounce copper. this current density corresponds to a self- heating effect of about 1.3w per square inch. the traces associated with the power path through the mosfets must have low resistance to maintain good efficiency and low drop. the resistance of 1-ounce copper is approximately 500? per square. lt c4371 4371f
15 for more information www.linear.com/LTC4371 a pplica t ions i n f or m a t ion figure 17. C36v to C72v/25a ideal diode-or 4371 f17 LTC4371 da db ga gb sa v z v dd sb v ss c1 2.2f r da 20k r db 20k m1 ipt020n10n3 m2 ipt020n10n3 v a ?36v to ?72v v b ?36v to ?72v v out 25a load d1 green led = mosfets good r z 30k r1 33k rtn faultb design example the following design example demonstrates the calcula- tions involved for selecting external components. consider a C 48v application with a C36v to C72v operating range, 200v peak transient and 25a maximum load current (see figure?17). the simplest configuration is chosen to power v dd , since this arrangement easily handles the operating conditions found in a C48v telecom power system. the bias resistor, r z , is calculated from equation 1: r z < 36v C 11.8v 750a = 32.2k? (9) the nearest lower 5% value is 30k. the worst case power dissipation in r z : p d(rz) = (72v C 11.8v) 2 30k = 166mw (10) a 30k 0.25w resistor is selected for r z . the maximum v z current is confirmed from equation 3 as a safe value of 2ma . a C200v transient pushes this to 6.3ma , safely below the maximum allowable v z current of 10ma. next, choose the n-channel mosfet. the 100v, ipt020n10n3 in a pg-hsof-8 package with r ds(on) ?=? 2m (max) offers a good solution. the maximum voltage drop across the mosfet is: ?v sd = 25a ? 2m? = 50mv (11) which is well below the 150mv minimum ?v sd fault threshold. from equation 7, the maximum power dissipation in the mosfet is: p d(mosfet) = 25a 2 ? 2m? = 1.25w (12) a reasonable value for the proposed package. the minimum recommended value of 20k is chosen for r da and r db . 20k protects the da and db pins to 300v. the led, d1 , requires at least 1ma of current to turn on fully; therefore, r1 is set to 33k to accommodate the mini - mum input supply voltage of C36v. the maximum current is 2ma at C72v, but excursions to 200v give 6ma, slightly beyond the faultb pin s 5ma capability. this means that if there is a fault present, a brief glitch might cause a no fault indication during a 200v transient. since d1 is a visual indicator, we ll accept the remote chance of a dim flash in exchange for the simple circuit solution. lt c4371 4371f
16 for more information www.linear.com/LTC4371 a pplica t ions i n f or m a t ion figure?18. C36v to C72v/25a ideal diode-or as a second design example, consider modifying the circuit of figure?17 to handle 300v transients and to drive a red led, which illuminates when a fault is present (see figure?18). r da and r db are sized to handle transients to 300v , so no change in their value is necessary. modifica - tions are necessary to drive the red led. a pzt a42 , a 300v npn with a minimum = 20 is chosen to supply both the led and the v dd pin. with a maxi - mum i dd of 9.5ma (LTC4371) + 1ma (led) = 10.5ma, equation?4 gives: i base = 10.5ma 20 = 525a (13) r z < 36v C 11.8v 50ua + 10ma 20 = 44k the nearest lower 5% value is 43k. to produce 1ma led current with variations in the circuit, r1 is chosen to be 8.2k. 4371 f18 LTC4371 da db ga gb sa v z v dd sb v ss r da 20k r db 20k m1 ipt020n10n3 m2 ipt020n10n3 v a ?36v to ?72v v b ?36v to ?72v v out 25a load d1 red led = mosfet bad r z 43k r1 8.2k rtn faultb q1 pzta42 c1 0.1f lt c4371 4371f
17 for more information www.linear.com/LTC4371 typical a pplica t ions figure?19. C36v to C72v single channel parallel application with 2 gate drive figure?20. C12v/100a application with 5ma gate pull-up enabled 4371 f19 LTC4371 da db ga gb sa v z v dd sb v ss r d 20k m1 ? m4 ipt020n10n3 v a ?36v to ?72v v out 100a load d1 green led = mosfets good r z 30k r1 33k rtn faultb 2.2f 4371 f20 LTC4371 da db ga gb sa v z v dd sb v ss faultb v a ?12v v b ?12v v out 100a load d1 green led = mosfets good r1 33k r2 100 c1 2.2f rtn m3 m1? m3 psmn0r9-3yld m1 m2 m6 m4 ? m6 psmn0r9-3yld m4 m5 *3psmn0r9-3yld lt c4371 4371f
18 for more information www.linear.com/LTC4371 typical a pplica t ions figure?21. C100v to C240v/5a ideal diode-or controller figure?22. C100v to C240v/5a ideal diode-or controller with open fuse and mosfet detection 4371 f21 LTC4371 da db ga gb sa v z v dd sb v ss faultb c1 2.2f m1 ipb200n25n3 m2 ipb200n25n3 v a ?100v to ?240v v b ?100v to ?240v v out 5a load d1 green led = mosfets good r z 120k r1 100k rtn m4 bsp89 d3 1n4148 m3 bsp89 d2 1n4148 4371 f22 f1 f2 q1 pzta42 LTC4371 da db ga gb sa v z v dd sb v ss faultb m1 ipb200n25n3 m2 ipb200n25n3 v a ?100v to ?240v v b ?100v to ?240v v out 5a load d1 green led = fuses/mosfets good r z 172k r1 100k rtn d2 mmsz5268btig c1 0.1f d3 mmsz5268btig m3 bsp129 m4 bsp129 rda 20k m5 bsp129 m6 bsp129 rdb 20k lt c4371 4371f
19 for more information www.linear.com/LTC4371 typical a pplica t ions 4371 f23 + 48v ct LTC4371 da db ga gb sa v z v dd sb v ss faultb c1 2.2f r da 20k r db 20k m1 ipt020n10n3 m2 ipt020n10n3 v a v b ? + d1 green led = mosfets good r z 10k r1 22k cl 41000f suncon me-wx 24vdc 4a 117vac figure?23. full wave center tap rectifier lt c4371 4371f
20 for more information www.linear.com/LTC4371 p ackage descrip t ion please refer to http://www.linear.com/product/4371#packaging for the most recent package drawings. msop (ms) 0213 rev f 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1 2 3 4 5 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8910 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 0.1016 0.0508 (.004 .002) ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661 rev f) lt c4371 4371f
21 for more information www.linear.com/LTC4371 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www.linear.com/product/4371#packaging for the most recent package drawings. 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev c 0310 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.70 0.05 3.55 0.05 package outline 0.25 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) pin 1 notch r = 0.20 or 0.35 45 chamfer lt c4371 4371f
22 for more information www.linear.com/LTC4371 ? linear technology corporation 2016 lt 0216 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTC4371 r ela t e d p ar t s typical a pplica t ion C48v ideal diode-or with fuse and open mosfet detection 4371 ta02 r db 20k f1 f2 LTC4371 da db ga gb sa v z v dd sb v ss faultb m1 ipt020n10n3 m2 ipt020n10n3 v a ?36v to ?72v v b ?36v to ?72v v out 25a load d1 green led = fuses/mosfets good r z 30k r1 33k rtn d2 1n4148w c1 2.2f d3 1n4148w r da 20k part number description comments ltc4354 negative voltage diode-or controller and monitor controls two n-channel mosfets, 1.2s turn-off, C80v operation ltc4355 positive voltage diode-or controller and monitor controls two n-channel mosfets, 0.4s turn-off, 80v operation ltc4357 positive voltage ideal diode controller controls single n-channel mosfet, 0.5s turn-off, 80v operation lt ? 4250 C48v hot swap controller active current limiting, supplies from C20v to C80v ltc4251/ltc4251-1/ ltc4251-2 C48v hot swap controllers in sot-23 fast active current limiting, supplies from C15v ltc4252-1/ltc4252-2/ ltc4252- a1/ ltc4252- a2 C48v hot swap controllers in ms8/ms10 fast active current limiting, supplies from C15v, drain accelerated response ltc4261/ltc4261-2 negative voltage hot swap controllers with adc and i 2 c monitoring 10-bit adc, floating topology, adjustable inrush lt c4371 4371f

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